Integrated circuits (ICs) typically comprise numerous circuit components, such as transistors, resistors and capacitors, interconnected to perform the desired functions. Strain generation in silicon has been proposed to improve carrier mobility of transistors which decreases trapped charges in the gate oxide. Stress inducing liners are used to induce stress. However, hot electrons are more mobile than hot holes. To compensate for the differences in mobility, different stresses are applied to the p-type and n-type transistors. Dual stress inducing liners can be used to induce different stresses in respective p-type and n-type transistors. For example, a compressive stress inducing nitride liner is provided over the p-type transistors while a tensile stress inducing nitride liner is provided over the n-type transistors.
Typically, one liner overlaps the other liner to ensure that no gaps exist between the two liners. At the region where the liners overlap, the thickness is about double that of the non-overlapping regions. The non-uniformity in thickness between the overlap and non-overlap regions creates problems in subsequent processes, which can lead to decreased reliability. Furthermore, typical dual liner processes involve use of more than one mask, for example two masks, during processing. This leads to process cost and product yield concerns.
From the foregoing discussion, it is desirable to provide improved dual liners which increase reliability as well as performance of ICs.